Technology Topics

Process technology

RIE Technology Supporting BiCS FLASH™

BiCS FLASH™ incorporates various innovative solutions to minimize the cost increase by changing the memory structure from 2D to 3D. For example, to fabricate BiCS FLASH™ memories, electrode and dielectric layers are alternately stacked all at once, and then holes are punched through all the layers at once, to reduce the number of manufacturing processes. The next step is the simultaneous deposition of dielectric films inside all the through-holes, followed by the formation of electrode columns. This structure causes the intersection of contiguous electrodes to form a memory cell (Figure 1). For these manufacturing processes, plasma etching (RIE*1) technology is crucial in order to form deep memory holes with a uniform diameter. To achieve the optimum hole shape, it is necessary to develop not only new mask materials and etching gases but also shape and plasma control technologies. We are working to further increase the number of layers by leveraging surface and gaseous layer control technologies as well as various simulation technologies.
 

*1 RIE: Reactive Ion Etching

Fig. 1: Formation of BiCS FLASH™ memory cells      Fig. 2: Underlying technologies for plasma etching

Fig. 1: Formation of BiCS FLASH™ memory cells      Fig. 2: Underlying technologies for plasma etching

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