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New Memory Cell Technology for Terabit-Scale High-Density Application

New memory cells are actively studied all over the world as a next generation non-volatile memory candidate with high-density and fast access speed. However, capacity of the memories developed so far is limited up to hundreds of gigabits. To overcome this limitation, we have evaluated the issues and solutions for achieving terabit-scale ultra-high density cross-point memory.

The challenge for achieving terabit-scale cross-point memory is to reduce operation current of a memory cell. Recent research pointed out that a memory cell with the operation current below mA is required to solve huge consumption current and voltage drop issues[1].

As a solution, we focused on a new non-volatile memory; Ag ionic memory. The ionic memory has a simple structure, consisting of an active metal and an insulator (Fig.1). The memory state can be controlled by generation and annihilation of a conductive filament in the insulator. By selecting an optimum combination of the active metal and insulator, the shape of the filament can be discontinuous clustered structure, reducing the operation current below mA.

Fig.1: Cross-sectional TEM image and switching mechanism for the Ag ionic memory cell.

Fig.1: Cross-sectional TEM image and switching mechanism for the Ag ionic memory cell.

We successfully fabricated a scaled cross-point array composed of the ionic memory cell (Fig.2) and demonstrated memory properties suitable for terabit-scale high-density applications (Fig.3).

Fig.2: Cross sectional TEM image for the scaled cross-point array composed of the Ag ionic memory cell.

Fig.2: Cross sectional TEM image for the scaled cross-point array composed of the Ag ionic memory cell.

Fig.3: Memory properties for the Ag ionic memory cells with various cell area.

Fig.3: Memory properties for the Ag ionic memory cells with various cell area.

This achievement was presented in the 2019 IEEE VLSI Technology Symposium[2].

[1] Z. Jiang, S. Qin, S. Fujii, D. Lee, S. Wong, and H.-S. P. Wong , “Selector requirements for Tera-bit Ultra-High-Density 3D Vertical RRAM”, 2018 IEEE Symposium on VLSI Technology, pp.107-108.

[2] S. Fujii, R. Ichihara, T. Konno, M. Yamaguchi, H. Seki, H. Tanaka, D. Zhao, Y. Yoshimura, M. Saitoh, and M. Koyama, “Ag Ionic Memory Cell Technology for Terabit-Scale High-Density Application”, 2019 IEEE Symposium on VLSI Technology, pp.T188-T189.

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