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HfO2-based Ferroelectric-Memory towards Low-Power and High-Density AI Applications

Recently, ferroelectric memories using ferroelectric-HfO2 film have attracted much attention towards low-power and high-density in-memory computing for AI (artificial intelligence). Typical ferroelectric memory devices are FeFET (Ferroelectric FET) which is a MIS*1FET with ferroelectric gate insulator and FTJ (ferroelectric tunnel junction) which is a ferroelectric film sandwiched by two electrodes. Among them, FeFET is especially promising thanks to high compatibility with CMOS LSI.

One of the issues in FeFET is small memory window (threshold voltage shift by polarization reversal in ferroelectric film). Although the limiting factors of memory window in FeFET have been studied so far [1], quantitative understanding is still insufficient.

In this work, we fabricated poly-Si channel FeFET with ferroelectric HfSiO (Fig.1). We extracted spontaneous polarization Ps in ferroelectric film and trap charge Qt at the interface between the ferroelectric film and SiO2 by newly developed technique where both gate current and drain current are measured during memory operation (Fig.2).

We found that a huge amount of trap charges generated at the interface cancels about 90% of spontaneous polarization (Fig.3), which is responsible for small memory window of around 1V (Fig.4).

This result is a major step for realization of high-performance FeFET towards AI applications.

This achievement was presented in the 2020 IEEE IEDM (International Electron Devices Meeting) as an invited talk [2]

This material is a partial excerpt and a reconstruction of the reference [2] © 2020 IEEE.

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Fig.1 : Cross-sectional TEM image of the fabricated poly-Si channel FeFET

Fig.1 : Cross-sectional TEM image of the fabricated poly-Si channel FeFET

Fig.2 : Schematic of our analysis technique of FeFET

Fig.2 : Schematic of our analysis technique of FeFET

Fig.3 : Extracted spontaneous polarization Ps and interface trap charge Qt

Fig.3 : Extracted spontaneous polarization Ps and interface trap charge Qt

Fig.4 : Measured drain current - gate voltage characteristics after program/erase

Fig.4 : Measured drain current - gate voltage characteristics after program/erase

*1….MIS: Metal Insulator Semiconductor

[1] K. Ni, P. Sharma, J. Zhang, M. Jerry, J. A. Smith, K. Tapily, R. Clark, S. Mahapatra, and S. Datta, “Critical Role of Interlayer in Hf0.5Zr0.5O2 Ferroelectric FET Nonvolatile Memory Performance,” IEEE Trans. Electron Devices, vol.65, no.6, pp.2461-2469 (2018).

[2] M. Saitoh, R. Ichihara, M. Yamaguchi, K. Suzuki, K. Takano, K. Akari, K. Takahashi, Y. Kamiya, K. Matsuo, Y. Kamimuta, K. Sakuma, K. Ota, and S. Fujii, “HfO2-based FeFET and FTJ for Ferroelectric-Memory Centric 3D LSI towards Low-Power and High-Density Storage and AI Applications”, 2020 IEEE IEDM, pp.375-378.

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