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Process technology

Profile control of memory hole etching based on mechanism elucidation

The formation of the memory hole using plasma etching technology*) is key to designing the memory cell for the next-generation BiCS FLASH™. It partially determines the number of stacked layers, which, in turn, establishes the storage density. Figure 1 shows the technical issues in the memory hole etching process [1]. Several issues can affect the etching profile, productivity and production yield. Here, we summarize our approach to controlling the etching profile of the memory hole. The memory hole is foundational for the BiCS FLASH™ structure; a perfect cylindrical shape is required to minimize variation of device performance. Many issues can lead to a deviation from the ideal shape such as bowing, striation, tapered profile, distortion of hole, and twisting. It is inherently difficult to analyze physical and chemical behavior of plasma-generated ions, radicals, and electrons inside a high-aspect-ratio hole. We seek to understand the involved mechanisms using an indirect, technical approach. For example, in order to investigate striation, we focused on the observation that a textured surface roughness can be created by glancing-angle ion irradiation. In Fig. 2 we show the construction of an apparatus that allowed us to experimentally simulate the sidewall bombardment from glancing-angle ions. We found the roughness depends on the surface material. It tended to be formed on deposited fluorocarbon byproducts rather than the silicon dioxide and nitride that make up the stack (Fig.3) From this result and further physical analyses about the etching profile, we proposed a model of striation formation on the sidewall in high-aspect-ratio holes as follows (Fig 4[2]).

(a) At first, a textured surface roughness is generated on the fluorocarbon film on the sidewall.
(b) This roughness is transferred to the dielectric films in a direction perpendicular to the direction of incident ions, as the hole diameter increases.
(c) This region of the roughness can move to deeper regions depending on the aspect ratio.

In this report, we introduced an example of a process analysis result using an experimental approach, but we are also active in plasma and etching profile simulation technology. We continue to accelerate our understanding of the process mechanisms in order to improve controllability in high-aspect-ratio hole formation. This work is critical for the development of next-generation high-performance BiCS FLASH™.

Fig.1. Issues in memory hole etching process [1].

Fig.1. Issues in memory hole etching process [1].

Fig.2. Simulated experiment using ion beam etching apparatus [2].

Fig.2. Simulated experiment using ion beam etching apparatus [2].

Fig.3. Material dependence on a textured surface roughness by Ar ion beam [2].

Fig.3. Material dependence on a textured surface roughness by Ar ion beam [2].

Fig.4. Formation model of striation in high-aspect ratio hole [2].

Fig.4. Formation model of striation in high-aspect ratio hole [2].

*) “RIE Technology Supporting BiCS FLASH™” in this Home Page

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Reference

[1] M. Omura et al., “High-Aspect-Ratio Hole Etching Process Using Reactive Plasma”, J. Plasma Fusion Res. Vol.97, No.9, 528-533 (2021).
[2] M. Omura et al., “Formation mechanism of sidewall striation in high-aspect-ratio hole etching”, Jpn. J. Appl. Phys. 58, SEEB02 (2019).

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